/*module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
    
    parameter IDLE = 10'b00_0000_0000;
    parameter S0 = 10'b00_0000_0001;
    parameter S1 = 10'b00_0000_0010;
    parameter S2 = 10'b00_0000_0100;
    parameter S3 = 10'b00_0000_1000;
    parameter S4 = 10'b00_0001_0000;
    parameter S5 = 10'b00_0010_0000;
    parameter S6 = 10'b00_0100_0000;
    parameter S7 = 10'b00_1000_0000;
    parameter S8 = 10'b01_0000_0000;
    parameter S9 = 10'b10_0000_0000;
    
    //parameter IDLE = 10'b00_0000_0000;
    parameter D_S0 = 10'b00_0000_0001;
    parameter D_S1 = 10'b00_0000_001x;
    parameter D_S2 = 10'b00_0000_01xx;
    parameter D_S3 = 10'b00_0000_1xxx;
    parameter D_S4 = 10'b00_0001_xxxx;
    parameter D_S5 = 10'b00_001x_xxxx;
    parameter D_S6 = 10'b00_01xx_xxxx;
    parameter D_S7 = 10'b00_1xxx_xxxx;
    parameter D_S8 = 10'b01_xxxx_xxxx;
    parameter D_S9 = 10'b1x_xxxx_xxxx;
    
    parameter OTHER_OUT = 2'b00;
    parameter S8_OUT = 2'b01;
    parameter S7_OUT = 2'b10;
    parameter S9_OUT = 2'b11;
    
    reg	[1:0]	out_reg;

    always @(state or in) begin
        casex(state)
            D_S0:begin
                next_state = in ? S1 : S0;
                //out_reg = OTHER_OUT;
            end
            D_S1:begin
                next_state = in ? S2 : S0;
                //out_reg = OTHER_OUT;
            end
            D_S2:begin
                next_state = in ? S3 : S0;
                //out_reg = OTHER_OUT;
            end
            D_S3:begin
                next_state = in ? S4 : S0;
                //out_reg = OTHER_OUT;
            end
            D_S4:begin
                next_state = in ? S5 : S0;
                //out_reg = OTHER_OUT;
            end
            D_S5:begin
                next_state = in ? S6 : S8;
                //out_reg = OTHER_OUT;
            end
            D_S6:begin
                next_state = in ? S7 : S9;
                //out_reg = OTHER_OUT;
            end
            D_S7:begin
                next_state = in ? S7 : S0;
                //out_reg = S7_OUT;
            end
            D_S8:begin
                next_state = in ? S1 : S0;
                //out_reg = S8_OUT;
            end
            D_S9:begin
                next_state = in ? S1 : S0;
                //out_reg = S9_OUT;
            end
            IDLE:begin
                next_state = state;
                //out_reg = OTHER_OUT;
            end
            default:begin
                next_state = S1;
                //out_reg = OTHER_OUT;
            end
        endcase
    end
    
    //assign {out2, out1} = out_reg;
    //assign {out2, out1} = (state == S9) ? S9_OUT : ((state == S8) ? S8_OUT : ((state == S7) ? S7_OUT : OTHER_OUT)); 
    
endmodule
*/

 
module top_module(
    input in,
    input [9:0] state,
    output [9:0] next_state,
    output out1,
    output out2);
    parameter s0=4'd0,s1=4'd1,s2=4'd2,s3=4'd3,s4=4'd4,s5=4'd5,s6=4'd6,s7=4'd7,s8=4'd8,s9=4'd9;
    assign next_state[s0] = ~in&(state[s0]|state[s1]|state[s2]|state[s3]|state[s4]|state[s7]|state[s8]|state[s9]);
    assign next_state[s1] = in&(state[s0]|state[s8]|state[s9]);
    assign next_state[s2] = in&(state[s1]);
    assign next_state[s3] = in&(state[s2]);
    assign next_state[s4] = in&(state[s3]);
    assign next_state[s5] = in&(state[s4]);
    assign next_state[s6] = in&(state[s5]);
    assign next_state[s7] = in&(state[s6]|state[s7]);
    assign next_state[s8] = ~in&(state[s5]);
    assign next_state[s9] = ~in&(state[s6]);
    
    assign out1 = state[s8]|state[s9];
    assign out2 = state[s7]|state[s9];
endmodule